Digital Design Flow in Cadence Virtuoso — From Schematic to Layout and Parasitic Extraction Using a CMOS Inverter (90 nm) I Md Ghalib Hussain

Digital Design Flow in Cadence Virtuoso: From Schematic to Layout and Parasitic Extraction (90 nm CMOS)

Based on a tutorial by Md Ghalib Hussain . This article explains the complete custom-design flow in Cadence Virtuoso using a simple yet fundamental block — the CMOS inverter.

Introduction

The CMOS inverter is the “Hello World” of analog and digital circuit design. Even though it seems simple, designing and analyzing an inverter in a professional EDA environment such as Cadence Virtuoso helps students understand the real-world flow used in semiconductor companies.

In this article, we will walk through the complete custom-design flow:

• Schematic design
• Symbol creation
• Testbench setup
• DC & transient simulations
• Layout design (90 nm gPDK)
• Design Rule Check (DRC)
• Layout vs Schematic (LVS)
• Parasitic extraction
• Post-layout simulation

This mirrors the exact workflow used inside industry — making it highly valuable for students, beginners, and engineers preparing for internships.

1. Schematic Design

The flow begins with drawing the inverter in the Virtuoso Schematic Editor. The inverter uses:

• One PMOS (pull-up)
• One NMOS (pull-down)

Key aspects students must understand:

• Device models come from the foundry PDK (in this case, 90 nm gPDK).
• W/L selection controls switching threshold and noise margins.
• Power rails (VDD, GND) must be correctly assigned.

Why schematic design matters?

This stage ensures your circuit is electrically correct. Before touching layout, the inverter must fully meet functional expectations. Students often skip this step, but professionals rely heavily on schematic-level simulation.

2. Creating a Symbol & Testbench

Once the schematic is complete, a symbol is generated. This allows the inverter to be instantiated in other circuits and testbenches.

In the testbench, the following elements are added:

• AC / transient input sources
• Load capacitance (C_L) — crucial for realistic delay
• Power rails

Simulations performed:

• DC Transfer Curve → VTC, switching threshold, noise margins
• Transient Simulation → rise/fall delays, propagation delay

3. Layout Design (Virtuoso Layout Suite)

Layout converts the schematic into a manufacturable geometric representation. For beginners, the CMOS inverter is the best starting point because it introduces:

• Diffusion regions
• Polysilicon gate formation
• N-well / P-well structures
• Contacts & vias
• Metal routing & spacing rules

The PDK enforces design rules — minimum widths, spacing, enclosure, and overlaps — that ensure manufacturability.

4. DRC — Design Rule Check

After layout, a DRC is run to ensure all geometries meet foundry rules. Common beginner errors:

• Poly spacing violations
• Metal enclosure issues
• Minimum width of diffusion
• Via enclosure violations

5. LVS — Layout vs Schematic

LVS ensures that the layout corresponds exactly to the schematic. If the layout connectivity doesn't match, the circuit will fail in silicon.

Common LVS issues:

• Incorrect net connection
• Transistor bulk not connected properly
• Mismatched device parameters

6. Parasitic Extraction (PEX)

Parasitics arise from:

• Interconnect resistance (R)
• Diffusion capacitances
• Gate overlap capacitances
• Coupling capacitances between metal layers

Extraction creates an annotated netlist with R, C components included. This step is essential because post-layout delay can be very different from schematic simulation.

7. Post-Layout Simulation

The final step is running simulations with parasitics included.

Observations typically include:

• Increased propagation delay
• Slight shift in switching threshold
• Slew rate degradation

This is the closest approximation to real silicon behavior.

Video Tutorial Series

This entire flow is explained beautifully by Md Ghalib Hussain in his YouTube playlist:

Watch YouTube Playlist →

Conclusion

Understanding the full custom design flow — from schematic to layout to post-layout simulation — is essential for anyone aiming for roles in VLSI Design, Physical Design, or AMS Circuit Design. The CMOS inverter provides the perfect foundation to learn industry-standard tools like Cadence Virtuoso.

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Credits: Tutorial and project by Md Ghalib Hussain. Article written for VLSIEdge by Afzal Malik.