Digital Design Flow in Cadence Virtuoso — From Schematic to Layout and Parasitic Extraction Using a CMOS Inverter (90 nm) I Md Ghalib Hussain

Digital Design Flow in Cadence Virtuoso: From Schematic to Layout and Parasitic Extraction (90 nm CMOS)

Based on a tutorial by Md Ghalib Hussain . This article explains the complete custom-design flow in Cadence Virtuoso using a simple yet fundamental block — the CMOS inverter.

Introduction

The CMOS inverter is the “Hello World” of analog and digital circuit design. Even though it seems simple, designing and analyzing an inverter in a professional EDA environment such as Cadence Virtuoso helps students understand the real-world flow used in semiconductor companies.

In this article, we will walk through the complete custom-design flow:

• Schematic design
• Symbol creation
• Testbench setup
• DC & transient simulations
• Layout design (90 nm gPDK)
• Design Rule Check (DRC)
• Layout vs Schematic (LVS)
• Parasitic extraction
• Post-layout simulation

This mirrors the exact workflow used inside industry — making it highly valuable for students, beginners, and engineers preparing for internships.

1. Schematic Design

The flow begins with drawing the inverter in the Virtuoso Schematic Editor. The inverter uses:

• One PMOS (pull-up)
• One NMOS (pull-down)

Key aspects students must understand:

• Device models come from the foundry PDK (in this case, 90 nm gPDK).
• W/L selection controls switching threshold and noise margins.
• Power rails (VDD, GND) must be correctly assigned.

Why schematic design matters?

This stage ensures your circuit is electrically correct. Before touching layout, the inverter must fully meet functional expectations. Students often skip this step, but professionals rely heavily on schematic-level simulation.

2. Creating a Symbol & Testbench

Once the schematic is complete, a symbol is generated. This allows the inverter to be instantiated in other circuits and testbenches.

In the testbench, the following elements are added:

• AC / transient input sources
• Load capacitance (C_L) — crucial for realistic delay
• Power rails

Simulations performed:

• DC Transfer Curve → VTC, switching threshold, noise margins
• Transient Simulation → rise/fall delays, propagation delay

3. Layout Design (Virtuoso Layout Suite)

Layout converts the schematic into a manufacturable geometric representation. For beginners, the CMOS inverter is the best starting point because it introduces:

• Diffusion regions
• Polysilicon gate formation
• N-well / P-well structures
• Contacts & vias
• Metal routing & spacing rules

The PDK enforces design rules — minimum widths, spacing, enclosure, and overlaps — that ensure manufacturability.

4. DRC — Design Rule Check

After layout, a DRC is run to ensure all geometries meet foundry rules. Common beginner errors:

• Poly spacing violations
• Metal enclosure issues
• Minimum width of diffusion
• Via enclosure violations

5. LVS — Layout vs Schematic

LVS ensures that the layout corresponds exactly to the schematic. If the layout connectivity doesn't match, the circuit will fail in silicon.

Common LVS issues:

• Incorrect net connection
• Transistor bulk not connected properly
• Mismatched device parameters

6. Parasitic Extraction (PEX)

Parasitics arise from:

• Interconnect resistance (R)
• Diffusion capacitances
• Gate overlap capacitances
• Coupling capacitances between metal layers

Extraction creates an annotated netlist with R, C components included. This step is essential because post-layout delay can be very different from schematic simulation.

7. Post-Layout Simulation

The final step is running simulations with parasitics included.

Observations typically include:

• Increased propagation delay
• Slight shift in switching threshold
• Slew rate degradation

This is the closest approximation to real silicon behavior.

Video Tutorial Series

This entire flow is explained beautifully by Md Ghalib Hussain in his YouTube playlist:

Watch YouTube Playlist →

Conclusion

Understanding the full custom design flow — from schematic to layout to post-layout simulation — is essential for anyone aiming for roles in VLSI Design, Physical Design, or AMS Circuit Design. The CMOS inverter provides the perfect foundation to learn industry-standard tools like Cadence Virtuoso.

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Credits: Tutorial and project by Md Ghalib Hussain. Article written for VLSIEdge by Afzal Malik.

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How to Build a Strong VLSI Portfolio While in College - by Afzal Malik

How to Build a Strong VLSI Portfolio While in College

A practical, experience-based guide for students who want to stand out in VLSI internships, placements, and research roles.

Why a VLSI Portfolio Matters More Than You Think

When I started my own VLSI journey, nobody told me that a portfolio is more important than your GPA. Not because grades aren’t important—they are—but because VLSI is a practical, design-driven field. Whether you're applying for an internship, a job, or even a research project, companies want proof that:

• You can think like an engineer.
• You can simulate, debug, and analyze circuits.
• You understand fundamentals beyond textbooks.
• You’ve touched real tools or built real mini projects.

A strong portfolio demonstrates all of this—without you saying a word.

What Exactly Is a VLSI Portfolio?

A VLSI portfolio is a collection of your work that shows your:

• Design skills (analog/digital)
• Simulation ability
• Understanding of concepts
• Project execution
• Documentation quality
• Problem-solving mindset

Think of it like a personal "design journal" that you publicly showcase using GitHub or a simple Google Drive folder + website.

Step 1: Start With 3–5 Solid Mini Projects

You don’t need a big SoC project. You just need simple but well-executed projects. Here are beginner-friendly yet impressive ones:

• CMOS Inverter Characterization – delay, power, noise margin
• Current Mirror Analysis – mismatch, output resistance
• Two-stage Op-Amp – gain, GBW, PM, stability
• 6T SRAM Bitcell – read/write operation explained
• Simple FIR Filter on FPGA – Verilog + testbench
• RC Delay Model – comparing theoretical vs simulated

Each mini project teaches something real. Interviewers love students who can articulate small concepts extremely well.

Step 2: Document Every Project Like an Engineer

Your documentation should contain:

1. Problem Statement — What you are building.
2. Theory Overview — Basics written in your own words.
3. Hand Calculations — Even if approximate.
4. Simulation Setup — Tools, models, parameters.
5. Results + Waveforms — Screenshots with labels.
6. Analysis — Why the results make sense.
7. Comparison — Theory vs simulation.
8. Conclusion — What you learned.

This is EXACTLY how engineers write design reports at companies like ST, Intel, Qualcomm, TI, and NXP.

Step 3: Use GitHub to Create a Clean Public Portfolio

GitHub is the industry gold standard. Recruiters love to see:

• neat folder structures
• proper naming
• clear README files
• version history
• organized simulation files

Your GitHub should have repositories like:

VLSI-Portfolio/
├── CMOS-Inverter/
│   ├── docs/
│   ├── simulations/
│   ├── README.md
├── OpAmp-Design/
├── Current-Mirror/
├── FIR-Filter-FPGA/
└── PLL-Notes/
      

This instantly sets you apart from 95% of students.

Step 4: Build a Simple Personal Website

It doesn’t have to be fancy. Even a Blogger or GitHub Pages site works. Your website should have:

• About Me — your background
• Projects — link your GitHub work
• Resume — internship-friendly version
• Articles — publish tutorials or reflections
• Contact

This shows maturity and communication ability—both highly valued in VLSI roles.

Step 5: Publish Articles Sharing What You Learn

Sharing knowledge is one of the strongest signals of confidence and understanding. Good topics for students:

• “How I simulated my first CMOS inverter”
• “What I learned building a current mirror”
• “5 things every VLSI student should know before starting cadence”
• “My experience debugging simulation errors”

These posts help others AND show recruiters you're serious.

Step 6: Build Depth in One Track

You don’t need to master everything. Pick ONE track:

• Analog
• Digital
• Physical Design
• Verification
• Memory

Then build 3–4 projects around that track. Engineers respect **depth over random breadth**.

Step 7: Showcase Everything When Applying

In your resume:

• Link GitHub
• Link personal website
• Add 2–3 strongest projects
• Share waveforms and analysis during interviews

Trust me — this makes interviewers take you seriously.

Final Checklist

• ☑ 3–5 mini projects documented
• ☑ GitHub repositories clean and public
• ☑ Simple personal website
• ☑ Articles explaining what you learned
• ☑ One chosen specialization
• ☑ Resume linked to projects

Conclusion

A good portfolio doesn’t require money, expensive tools, or special labs. It requires consistency, curiosity, and documentation. Start small. Build mini projects. Share your learning. Within 6 months, you’ll look completely different from the crowd—and companies will notice.

Written by: Afzal Malik

© VLSIEdge — Your edge in VLSI, chip design & semiconductors.

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